On Retiming for FPGA Logic Module Minimization

Y. P. Chen and D. F. Wong Department of Computer Sciences The University of Texas at Austin Austin, Texas 78712 Abstract In this paper, we consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a ipop is the only destination of its driving combinational block, then both the ipop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of registers that can not be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program.